首页> 外文会议>European Solid-State Device Research Conference;ESSDERC; 20070911-13;20070911-13; Muenchen(DE);Muenchen(DE) >Demonstration of phase-controlled Ni-FUSI CMOSFETs employing SiON dielectrics capped with sub-monolayer ALD HfSiON for low power applications
【24h】

Demonstration of phase-controlled Ni-FUSI CMOSFETs employing SiON dielectrics capped with sub-monolayer ALD HfSiON for low power applications

机译:演示了相控Ni-FUSI CMOSFET,该晶体管采用SiON电介质覆盖的亚单层ALD HfSiON,适用于低功耗应用

获取原文
获取原文并翻译 | 示例

摘要

In this work, by employing a sub-monolayer HfSiON cap (via ALD deposition) on the SiON host dielectrics in the phase-controlled Ni-FUSI CMOS devices, we report that 1) the devices (both n-FETs and p-FETs) V_t is effectively modulated likely due to the Fermi-level pinning relaxation; 2) the gate leakage is significantly reduced; 3) the dielectrics reliability characteristics (such as TZBD, pFETs NBTI, and nFETs PBTI) are clearly improved; 4) both the gate capacitance equivalent thickness (T_(inv)) and the long channel device high E_(eff) mobility are preserved. High-V-t ring oscillator with a delay of 17ps has been demonstrated, showing a much-reduced static power (~10 times) as compared to the devices using the pure SiON dielectrics. It is proposed that the SiON dielectrics capped with sub-monolayer HfSiON, in combination with the phase-controlled Ni-FUSI technology, is promising for 45nm and beyond low power CMOS applications.
机译:在这项工作中,通过在相控Ni-FUSI CMOS器件的SiON主体电介质上采用亚单层HfSiON帽(通过ALD沉积),我们报告了1)器件(n-FET和p-FET) V_t可能由于费米能级钉扎弛豫而得到有效调制; 2)栅极泄漏大大减少; 3)介电可靠性特性(例如TZBD,pFET NBTI和nFET PBTI)得到明显改善; 4)既保留了栅极电容的等效厚度(T_(inv)),又保留了长沟道器件的高E_(eff)迁移率。已经证明了具有17ps延迟的高V-t环形振荡器,与使用纯SiON电介质的器件相比,其静态功耗大大降低(约10倍)。有人提出,用亚单层HfSiON覆盖的SiON电介质与相控Ni-FUSI技术相结合,有望在45nm及以后的低功耗CMOS应用中使用。

著录项

相似文献

  • 外文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号