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Dual gate dielectric scheme: SiON for high performance devices and high K for low power devices
Dual gate dielectric scheme: SiON for high performance devices and high K for low power devices
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机译:双栅极介电方案:用于高性能器件的SiON和用于低功率器件的高K
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摘要
A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.
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