DISCREPANCIES OF THE FLAT-BAND VOLTAGE MODELS REVEALED BY SIMULATIONS IN SUB-50nm SOI FILMS

摘要

The flat-band voltage is a key parameter in the electrical characterization of the SOI wafers. The usual models for the flat-band voltage were established for SOI structures with 2μm-0.2μm Si-film thickness and 40-20nm front oxide thickness. The electric charge from the buried oxide was poorly investigated, because the interesting conduction occurs in the vicinity of the front oxide. But the pseudo-MOS transistor, used as a dedicated device for electrical characterization, exclusively works with buried oxide. The classical model of V{sub}(FB), deduced for the pseudo-MOS transistors with micronic sizes, presents some deficiencies in the nanodevice area. The downscaling consequences of the SOI wafers on the flat-band voltage modeling were studied in this paper. The simulations and modeling were focused on the electric charges arisen at Si/SiO{sub}2 /Si interfaces.