Application of logic mapping in the low voltage functional failure analysis

摘要

Logic mapping is shown to be a good debug technique to increase the PFA success rate in logic failures, especially low voltage functional failures. The faster cycle time in PFA is especially critical in today fast product yield ramp up. The results from this paper demonstrated that logic mapping is capable of isolating hard defects, which cause functional failures at all voltages in advance CMOS devices. Furthermore, we demonstrated that logic mapping is also capable of isolating VLV related failures as well.