The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies has led to dramatic increases in mask costs, pushing prototype and low volume production designs to the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such low volume designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle design and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works on wafer dicing do not take in account several known degrees of freedom and requirements, which degrades the optimality and feasibility of the proposed solutions. Furthermore, the delay cost associated with schedule alignment has been completely ignored in all previous works. In this paper we propose an enhanced MPW flow comprising four main steps: (1) schedule-aware project partitioning, (2) multi-project reticle floorplanning, (3) wafer shot-map definition, and (4) wafer dicing plan definition. The proposed project partitioning algorithm gives improved trade-offs between mask cost and schedule delay cost. Our reticle floorplaner combines hierarchical quadrisection with a simulated annealing framework to generate more "diceable" floorplans subject to given maximum reticle sizes. The round wafer shot-map definition step maximizes extraction of functional dies from partially printed reticle images. Finally, our dicing planner employs multiple side-to-side dicing plans for different wafers, as well as different reticle image rows/columns within a wafer. Experiments on industry testcases show that our methods significantly outperform not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.
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