High-performance processors use data-speculation to reduce the execution time of programs. Data-speculation depends on some kind of prediction, and allows the speculative execution of a chain of dependent instructions. On a misprediction, a recovery mechanism must reissue the speculatively issued instructions. Some recovery mechanisms rely on keeping each instruction in the Issue Queue (IQ) until it is known that the instruction has used correct data. However, their authors either assume that the IQ and the Reorder Buffer (ROB) are unified, or do not detail how the instructions are removed from the IQ before reaching the ROB head entry. We propose the Verification Issue Queue (VIQ), a mechanism fed with a verification flow graph; the VIQ decides if an instruction can either be removed from the IQ or must be re-issued; the VIQ also allows decoupling the IQ from the ROB. Our evaluations, in the context of load address prediction, show that the verification mechanism is crucial for exploiting the performance potential of data speculation, and that the kind of graph used by the VIQ has a performance impact similar to reducing first-level cache latency by one cycle.
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