Generation of Test Data for Verification of Caching Mechanisms and Address Translation in Microprocessors

摘要

This paper considers the problem of test data generation for the core-level verification of microprocessors; namely, the problem of constructing a test program on the basis of its abstract form (test template). To solve this problem, we propose an algorithm reducing it to a problem of resolving constraints. This paper addresses the verification of memory-handling instructions (taking into account such microprocessor features as caching and address translation).