Analysis of a Wafer Overlay Projection Algorithm for use in Lot Disposition

摘要

The decision to rework a wafer, or a batch of wafers, is based on the expectation that the resulting quality of the reprocessed wafers will be better and produce higher yield. For lot disposition specific to layer-to-layer registration, the decision criteria are generally based on a comparison of recorded overlay errors to tolerances or specifications established during design of the device. In most fabrication facilities the mean and standard deviations of the measured overlay is used to monitor the lithography process and the "Mean + 3 Sigma" parameter used as an estimation of the maximum registration error. However, this procedure is conservative and typically overestimates the maximum error, potentially resulting in excess rework. In this paper a novel approach to lot dispositioning is outlined and analyzed. With this procedure the wafers are measured using a standard sampling map, the systematic grid and field errors modeled and residuals resolved. The systematic errors are then projected over the wafer to each die location, establishing a registration offset for each device. Random errors are estimated by applying the distribution of residual data to each of the projected error vectors. This creates a distribution of possible registration errors for each device within the wafer and a comparison of these to product specifications is used to develop a probability assessment whether each die will meet process overlay requirements. This procedure is supported by a commercially ava ilable software package developed by itemic, AG and based on 3 months of production data, the effectiveness of this disposition criterion on prediction of wafer yield, will be presented. As this technique models the systematic errors and projects them across each wafer it can be extended to prediction of the best achievable overlay if wafers were reworked. This "corrected" analysis is then used as a gauge in determining if reworking makes sense, reducing rework cycles of problem lots with non-correctable errors such as those with wafer warpage.