Analysis of a Wafer Overlay Projection Algorithm for usein Lot Disposition

摘要

The decision to rework a wafer, or a batch of wafers, is based on the expectation that thernresulting quality of the reprocessed wafers will be better and produce higher yield. Forrnlot disposition specific to layer-to-layer registration, the decision criteria are generallyrnbased on a comparison of recorded overlay errors to tolerances or specificationsrnestablished during design of the device. In most fabrication facilities the mean andrnstandard deviations of the measured overlay is used to monitor the lithography processrnand the "Mean + 3 Sigma" parameter used as an estimation of the maximum registrationrnerror. However, this procedure is conservative and typically overestimates the maximumrnerror, potentially resulting in excess rework.rnIn this paper a novel approach to lot dispositioning is outlined and analyzed. With thisrnprocedure the wafers are measured using a standard sampling map, the systematic gridrnand field errors modeled and residuals resolved. The systematic errors are then projectedrnover the wafer to each die location, establishing a registration offset for each device.rnRandom errors are estimated by applying the distribution of residual data to each of thernprojected error vectors. This creates a distribution of possible registration errors for eachrndevice within the wafer and a comparison of these to product specifications is used torndevelop a probability assessment whether each die will meet process overlayrnrequirements. This procedure is supported by a commercially ava ilable software packagerndeveloped by itemic, AG and based on 3 months of production data, the effectiveness ofrnthis disposition criterion on prediction of wafer yield, will be presented. As thisrntechnique models the systematic errors and projects them across each wafer it can bernextended to prediction of the best achievable overlay if wafers were reworked. Thisrn"corrected" analysis is then used as a gauge in determining if reworking makes sense,rnreducing rework cycles of problem lots with non-correctable errors such as those withrnwafer warpage.