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The Effects of Doping Impurity on Dislocation Generation in InP Semiconductor Crystals

机译:掺杂杂质对INP半导体晶体脱位发电的影响

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Dislocations in indium phosphide (InP) single crystals are generated by excessive stresses induced during the crystal growth process and the fabrication and packaging of microelectronic devices/circuits. The presence of dislocations has adverse effects on the performance and reliability of the InP-based devices/circuits. It is well known that dislocation density can be significantly reduced by doping impurity atoms into InP crystal during its growth, fabrication and packaging processes. A viscoplastic constitutive equation that couples a microscopic dislocation density with a macroscopic plastic deformation is employed in a transient finite element model for calculating the dislocation density generated in InP crystal during its growth, fabrication and packaging processes. The dislocation density is considered as an internal state variable and the doping impurity is represented by a drag-stress in this constitutive equation. An InP single crystal grown by the vertical gradient freeze (VGF) process is adopted as an example to study the influences of doping impurity on dislocations generated in the grown crystal. The calculated results show that doping intermediate level (~10~(17)of Ge atoms per cm~3, ~10~(18)of S atoms per cm~3) of Ge and S can significant reduce dislocation generation and produces dislocation free InP crystal except the outer edge.
机译:在磷化铟位错(INP)单晶通过在晶体生长过程和制造诱导和微电子器件/电路的包装过度应力产生。位错的存在对InP基器件/电路的性能和可靠性产生不利影响。它公知的是位错密度可通过其生长,在制造过程中掺杂杂质原子引入的InP晶体和包装工艺显著降低。耦合用宏观塑性变形的微观位错密度在瞬态有限元模型被用于其生长,在制造过程中计算的InP晶体中产生的位错密度和包装过程甲粘塑性本构方程。的位错密度被认为是作为内部状态变量,并且所述掺杂杂质是通过在本构方程拖应力表示。由垂直梯度凝固生长在InP单晶(VGF)工艺被采用作为一个例子,研究了在生长的晶体产生的位错的掺杂杂质的影响。所计算出的结果表明,掺杂中间水平(〜每厘米〜3,10〜葛(17)原子〜每厘米〜3 10〜S的(18)个原子)的Ge和S可显著减少位错产生,并产生无位错的InP晶体以外的外边缘。

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