Embedded trench DRAMs for sub-0.10μm generation by using hemispherical-grain technique and LOCOS collar process

摘要

Recently, embedded DRAM is a key device for logic LSI. The trench DRAM is more suitable for the logic LSI than the stacked DRAM[1], because the multi-level interconnect of the trench DRAM is fabricated more easily and cheaper than the stacked one. Moreover, since the stacked DRAM needs high-k capacitor, the COO is very high for the capacitor process and a huge investment is necessary. In this paper, we propose the trench capacitor scaling strategy. The strategy is realized by the LOCOS collar process, the HSG technique and so on. The LOCOS collar process reduces the COO and RPT of the trench capacitor with little investment. The HSG technique assures the enough capacitance without the high-k capacitor.