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Effect of electrical stress on the Al2O3-based 4H-SiC MOS capacitor with a thin SiO2 interface buffer layer

机译:电应力对基于Al2O3的4H-SiC MOS电容器的影响薄SiO2接口缓冲层

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The effect of electrical stress on the Al2O3-based n-4H-SiC metal oxide semiconductor (MOS) capacitor with a thin SiO2 interfacial buffer layer (IBL) has been investigated. The electrical characteristics of MOS capacitors have been measured using capacitance-voltage (C-V), current-voltage (I-V) and charge trapping behavior of the films under constant voltage stressing (CVS) to understand the reliability and the interface trapping characteristics of Al2O3/SiO2/n-4H-SiC gate stack. It is found that Al2O3/SiO2 stack layer has lower positive charge generation and smaller flatband voltage shift under constant voltage stressing, which exhibits an excellent interface quality and high dielectric reliability making this structure suitable for 4H-SiC power devices applications.
机译:用薄SiO 2 2 O 3 基于N-4H-SIC金属氧化物半导体(MOS)电容的影响 >已经研究了界面缓冲层(IBL)。 使用电容 - 电压(CV),电流 - 电压(IV),电流 - 电压(IV)和恒定电压应力(CV)的电流 - 电压(IV)和电荷俘获行为来测量MOS电容器的电特性,以了解AL 2 O 3 / SIO 2 / N-4H-SIC栅极堆叠。 发现Al 2 O 3 / SIO 2 堆叠层具有较低的正电荷产生和恒定电压应力下的较小的漏带电压变换,这 展示出色的界面质量和高介电可靠性,使得适用于4H-SIC电源装置的结构。

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