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Determination of Surface Depletion Thickness of p-doped Silicon Nanowires Synthesized Using Metal Catalyzed CVD Process

机译:使用金属催化CVD工艺合成P掺杂硅氧化硅纳米线表面耗尽厚度的测定

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An in-depth understanding of the distribution and impact of doping in nanowires is crucial for the rational design of future nanowire based devices synthesized using bottom-up techniques. We used a very slow wet chemical etchant for progressive reduction of the diameters of boron-doped, metal-catalyzed silicon nanowires with diverse diameters and lengths. The low temperature process helped avert the dopant segregation which is common in high temperature processes such as oxidation for diameter reduction. We ensured identical surface conditions subsequent to diameter reduction with wet-chemical etching and, using DC current-voltage measurements, found the resistance to increase with decreasing diameter. As the diameters were shrunk from a larger diameter to approx 50 nm in diameter, they exhibited a strong non-linear increase of the resistance indicating complete depletion of the cross-section caused by surface charges. The dopant concentration of the nanowires was calculated to be 2.1 X 10~(19) cm~(-3) and the corresponding surface charge density was around 2.6 X 10~(12) cm~(-2).
机译:深入了解纳米线中掺杂的分布和影响对于使用自下而上技术合成的未来纳米线的设备的合理设计至关重要。我们使用了一个非常缓慢的湿化学蚀刻剂,用于逐渐降低硼掺杂的金属催化硅氧化硅纳米线的直径,具有多样化的直径和长度。低温过程有助于避免掺杂剂的偏析,其在高温过程中常见,例如氧化直径减小。我们确保了随着湿化学蚀刻直径减小后的相同表面条件,并且使用直流电流电压测量,发现直径减小的电阻增加。随着直径从直径的直径缩小到直径大约50nm的直径,它们表现出强烈的非线性增加的电阻,表明由表面电荷引起的横截面完全消耗。纳米线的掺杂剂浓度计算为2.1×10〜(19)cm〜(-3),相应的表面电荷密度为约2.6×10〜(12)cm〜(-2)。

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