The paper presents a kind of test patterns generation scheme for BIST with multiple scan chains. In the scheme the pseudo-random pattern generator is implemented by an LFSR and shifts the bit sequences into all scan chains simultaneously. A method of constructing multiple scan chains is proposed to overcome the bad effect on fault coverage due to the correlation between scan chains. Furthermore the minimum set of deterministic patterns is generated for hard-to-test faults by ATPG, which is used to design the bit modifying logic circuit. Then the complete fault coverage is obtained by modifying the test patterns at certain bit positions.
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