Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring

机译：具有TSVS（通过硅通孔）和微型多层布线的硅插入器

获取原文

页面导航

摘要
著录项
引文网络
相似文献
相关主题

摘要

In order to achieve high density and high performance package, through silicon vias (TSVs) technology has been desired. Our purpose is the development of silicon interposer which has TSVs and fine multilayer Cu wiring on both side. Since silicon substrate

机译：为了实现高密度和高性能封装，需要通过硅通孔（TSV）技术。我们的目的是在两侧具有TSV和微型多层Cu布线的硅插入器的开发。由于硅衬底

著录项

来源
《Electronic Components and Technology Conference》|2008年||共6页
会议地点
作者
Sunohara M.; Tokunaga T.; Kurihara T.; Higashi M.;
展开▼
作者单位

展开▼
会议组织
原文格式 PDF
正文语种
中图分类 TN6-53;
关键词
copper; elemental semiconductors; integrated circuit interconnections; modules; silicon; Si; fine multilayer wiring; inorganic-organic hybrid substrate; interconnection; interlayer dielectric; silicon interposer; silicon module; thermal expansion coefficient; through;

机译：铜;元素半导体;集成电路互连;模块;硅;Si;精细多层布线;无机 - 有机混合衬底;互连;层间电介质;硅式膜;硅模块;热膨胀系数;通过;

相似文献

外文文献
中文文献
专利

1. Fabrication and electrical characteristics of a novel interposer with polymer liner and silicon pillars with ultra-low-resistivity as through-silicon-vias (TSVs) for 2.5D/3D applications [J] . Chen Qian-Wen, Yan Yang-Yang, Ding Ying-Tao, Microsystem technologies . 2015,第10期

机译：一种新型的中介层的制造和电学特性，该中介层具有用于2.5D / 3D应用的具有超低电阻率的直通硅通孔（TSV）的聚合物衬里和硅柱
2. Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon [J] . Sukumaran V., Kumar G., Ramachandran K., Components, Packaging and Manufacturing Technology, IEEE Transactions on . 2014,第5期

机译：具有与硅中的TSV相同间距的直通封装的超薄3-D玻璃中介层的设计，制造和表征
3. Use of Hard Mask for Finer (<10 μm) Through Silicon Vias (TSVs) Etching [J] . Choi Somang, Hong Sang Jeen Transactions on Electrical and Electronic Materials . 2015,第6期

机译：使用硬掩模通过硅通孔（TSV）刻蚀更精细（<10μm）
4. Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring [C] . Sunohara M., Tokunaga T., Kurihara T., Electronic Components and Technology Conference . 2008

机译：具有TSVS（通过硅通孔）和微型多层布线的硅插入器
5. Analytical Characterization of Electrolyte and Additives for High Quality Copper Plating of Through Silicon Vias (TSVs) [D] . Wu, Hailong. 2013

机译：硅通孔（TSV）的高质量镀铜的电解质和添加剂的分析特性
6. Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon–Germanium Multilayers Structures for Vertical Transistors Application [O] . Chen Li, Hongxiao Lin, Junjie Li, 2020

机译：用于垂直晶体管应用的磷掺杂硅/硅锗多层结构的生长和选择性蚀刻
7. Use of Hard Mask for Finer (<10 μm) Through Silicon Vias (TSVs) Etching [O] . Somang Choi, Sang Jeen Hong 2015

机译：通过硅通孔（TSV）蚀刻更精细地（<10μm）的硬掩模

Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring

摘要

著录项

引文网络

相似文献

相关主题

期刊订阅