Ultra-shallow source/drain junctions for nanoscale CMOS usingselective silicon-germanium technology

摘要

Future CMOS technology nodes bring new challenges to formation ofsource/drain junctions and their contacts to limit their seriesresistance contribution to ten percent of the device channel resistance.This requires not only extremely low junction sheet resistance valuesbut also super abrupt doping profiles and contact resistivities that cannot be obtained with the existing self-aligned silicide technology. Inthis paper, we present an overview of the SiGe junction technologydesigned to meet the demands of the future technology nodes down to 30nm. The technology is based upon selective deposition of boron orphosphorus doped SiGe in source/drain areas isotropically etched to thedesired junction depth. The technology is limited to temperatures below800° C. Hence; it is also compatible with future high-κ gatestacks, which can not withstand higher temperatures. The resultsindicate that the technology offers great promise in meeting the demandsof the end-of-the-roadmap devices