Throughput enhancement strategy of maskless electron beam directwriting for logic device

摘要

A pattern design method for semiconductor circuits in logic devicewas developed, which realized an electron beam (EB) exposure withsufficient throughput. The number of EB shots can be decreased byrepeating logic synthesis and P and R (place and route) by removingusable standard cells (SCs). By using the design method, a functionalblock with about 140 kGates could be generated with only 17 SCs, and theminimum number of EB shots was attained with 24 SCs. The increase in thetotal area of SCs and the consumed power of the chip was only 10%