Hot carrier reliability considerations in the integration of dualgate oxide transistor process on a sub-0.25 μm CMOS technology forembedded applications

摘要

The competing effects of the well (super steep versus uniformchannel) and the source/drain (LDD) structures are analyzed on the hotcarrier degradation of 90 Å, 3.3V I/O transistor integrated on a0.25 μm, 1.8 V technology with a high performance 35 Å, 1.8 Vcore transistor. The cost vs. reliability trade offs in the dual gateoxide integration are discussed