Dual polycide gate and dual buried contact technologies achieving a0.4 μm nMOS/pMOS spacing for a 7.65 μm2 full-CMOS SRAMcell

摘要

An enlarged grain dual polycide gate and a dual buried contacttechnology using regrown amorphous-Si have been developed for highdensity full-CMOS SRAM cell. Lateral dopant diffusion has beensuppressed to be less than 0.2 μm, as a result, 0.4 μm nMOS/pMOSspacing was realized using an 850° C process. This technology canalso achieve dual buried contact with low resistance and suppress gatedepletion simultaneously. A 7.65 μm2 full-CMOS cell using0.35 μm design rule has been realized and superior cell stability at1.5 V operation has been confirmed