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PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies

机译：低于65纳米CmOs技术的pmOs专用睡眠开关双阈值电压多米诺逻辑

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Zhiyu Liu; Student Member; Volkan Kursun;
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年度 2016
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1. PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies [J] . Zhiyu Liu, Kursun V. IEEE transactions on very large scale integration (VLSI) systems . 2007,第12期

机译：低于65nm CMOS技术的仅PMOS睡眠开关双阈值电压Domino逻辑
2. Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits [J] . Shah Ambika Prasad, Neema Vaibhav, Daulatabad Shreeniwas, Microsystem technologies . 2019,第5期

机译：双阈值电压和睡眠开关双阈值电压Domino逻辑电路泄漏减少方法
3. Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current [J] . Zhiyu Liu, Volkan Kursun Microelectronics journal . 2006,第8期

机译：具有降低的亚阈值和栅极氧化物泄漏电流的睡眠开关双阈值电压多米诺逻辑
4. A contention-free domino logic for scaled-down CMOS technologies with ultra low threshold voltages [C] . Elraba, M.E.S., Anis, . 2000

机译：具有超低阈值电压的按比例缩小CMOS技术的无竞争多米诺逻辑
5. High Voltage Switching with Conventional CMOS Transistors [D] . Ning, Runtao. 2018

机译：具有传统CMOS晶体管的高压切换
6. A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process [O] . Meng-Yin Hsu, Chu-Feng Liao, Yi-Hong Shih, 2017

机译：采用纯CMOS逻辑工艺的具有自抑制电阻切换负载的RRAM集成4T SRAM
7. Sleep Switch Dual Threshold Voltage Domino Logic with Reduced Standby Leakage Current [O] . Kursun, Volkan, Friedman, Eby G. 2004

机译：具有减小的待机漏电流的睡眠开关双阈值电压Domino逻辑

PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies

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