A 7-Nm Dual Port 8T SRAM with Duplicated Inter-Port Write Data to Mitigate Write Disturbance

摘要

Two read-write 8T dual port static random accessmemories (SRAMs) suffer write disturb issue when both of its ports are accessed simultaneously. Write disturb is detrimental at low voltages in deep submicron technologies due to increased variations. This paper proposes a duplicated inter-port write data to mitigate write disturb in dual port SRAM design targeted on 7-nm FinFET TSMC technology. We have implemented duplicated inter-port write by employing two NMOS switches per bit line. We choose moderate sizes for these switches to have abalanced trade-off between area and duplication of inter-port write data. With NMOS switch size of nfin=4, we significantly suppress the write disturb and improve the write time by 2.16x at low voltage of 0.63V. Moreover, at further low voltages of 0.585V and 0.54V, our design achieves write time improvement over single port access.