Design Insights to Address Low Current ESD Failure and Power Scalability Issues in High Voltage LDMOS-SCR Devices

摘要

Power-scalability issues for longer pulse duration discharges (PW>100ns) in high voltage LDMOS-SCR devices is evaluated. The severity of the problem with increasing LDMOS voltage classes is highlighted with a need for newer design strategies. A systematic design approach is presented to evaluate the effect of different design parameters on LDMOS filament and SCR turn-on near the snapback region. Finally design guidelines are presented to improve the power scalability without compromising on its ON-state DC (functional) and Safe Operating Area (SOA) characteristics.