EMBEDDED HIGH-VOLTAGE LDMOS-SCR DEVICE HAVING STRONG VOLTAGE CLAMPING AND ESD ROBUSTNESS

摘要

An embedded high-voltage LDMOS-SCR device having strong voltage clamping and ESD robustness, which can be used for on-chip ESD protection for a high-voltage IC. The device is mainly composed of a P substrate (101), a P-well (102), an N-well (103), a first field oxide isolation region (104), a first P+ injection region (105), a second field oxide isolation region (106), a first N+ injection region (107), a first fin polysilicon gate (108), a second N+ injection region (109), a second fin polysilicon gate (110), a third N+ injection region (111), a third fin polysilicon gate (112), a polysilicon gate (113), a fourth fin polysilicon gate (114), a second P+ injection region (115), a fifth fin polysilicon gate (116), a third P+ injection region (117), a sixth fin polysilicon gate (118), a fourth P+ injection region (119), a third field oxide isolation region (120), a fourth N+ injection region (121) and a fourth field oxide isolation region (122). The device, under the action of an ESD pulse, can form a resistance-capacitance coupling current path with an embedded NMOS interdigitated structure at a source end and an embedded PMOS interdigitated structure at a drain end and an ESD current discharge path with an LDMOS-SCR structure, thereby enhancing the ESD robustness of a device and improving the voltage clamping performance.