A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS

摘要

This paper presents a 36 GS/s data path that is based on CMOS logic. The proposed non-clocked delay generator achieves high bandwidth as well as produces near-1-UI delay by employing digitally controlled cross-coupled latches. In addition, the proposed 4-to-2 serializer with pre-charging/discharging transistors not only reduces a data-dependent jitter but also mitigates non-ideal effects such as charge injection and clock feedthrough by removing the floating nodes of the multiplexer. As a result, the 8-to-2 serializer has extremely low rms jitter of 146 fs and peak-to-peak jitter of 980 fs at the output node. Moreover, thanks to the simple architecture of the 8-to-2 serializer and the delay generator, power consumption is remarkably reduced. The data path that dissipates 21.87 mW from 1.2-V supply is implemented and laid-out in 28-nm CMOS technology.