Accurate 3-D capacitance extractions for advanced nanometer CMOS nodes

摘要

During the R&D of advanced nanometer CMOS technologies such as 20nm and beyond, we implemented in-house 3-D capacitance extraction software to provide R&D engineers with an accurate modeling tool to optimize the complex 3-D nanometer dimensions and materials that may be used for competitive CMOS devices in terms of power consumption, performance, and area. Our extractor solves 3-D Laplace's equation and extracts capacitances and resistances targeting accurate on-chip parasitic modeling. In essence, the numerical method we adopted features flexible grids for arbitrary shapes in nanometer CMOS devices. Robust and rigorous algorithms are described that allow the R&D engineers to monitor the convergence and specify the corresponding accuracy level based on the resource and allowed turnaround time.