A 160 MS/s, 11.1 mW, single-channel pipelined SAR ADC with 68.3 dB SNDR

摘要

A low-power, 160 MS/s, single-channel pipelined SAR ADC is presented. The ADC frontend employs two capacitive DACs that decouple the high-speed SAR operation from the low-noise residue generation, thereby improving both speed and power dissipation. Measured results show an SNDR of 68.3/66 dB at low frequency/Nyquist inputs, respectively, which corresponds to a FOM of 167/164.7 dB. The converter core occupies 0.09 mm in 65-nm CMOS.