Lower trigger voltage design for ESD protection device applied in PMIC application

摘要

Lower trigger voltage ESD protection has been designed in PMIC application process. The proposed design lowers trigger voltage around 11% without extra mask layer and the layout diagram is simple and clear. The proposed device can be turned on quickly to protect the large array in output buffer design safely. It sustains 3.8kV human-body-model (HBM) and 350V machine model (MM) ESD tests, respectively.