Electrical Properties and Interfacial Structures of High-k/Metal Gate MOSCAP using Ti/TiN Scavenging Stack between High-k Dielectric and Metal Gate

摘要

High permittivity materials have been required to replace traditional SiO_2 to be gate dielectric to extend Moore's law. However, growth of a thin SiO_2-like interfacial layer (IL) is almost unavoidable during the deposition or subsequent high temperature anneal. This limits the scaling benefits of incorporating high-k dielectrics into transistors. A promising approach, in which O-scavenging metal layer and a barrier layer preventing scavenging metal diffusing into high-k gate dielectric are used to engineer the thickness of the IL, is reported in this paper. Using a Ti scavenging layer and TiN barrier layer on HfO_2 dielectric, the equivalent oxide thickness (EOT) decreased due to the effect of O-scavenging indicated by the C-V measurement results. From high resolution transmission electron microscopy (HRTEM) pictures and X-ray photoelectron spectroscopy (XPS), the removal of interfacial layer (IL) has been seen clearly.