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Effective Approach for TSV Cu Plating Gap Fill Improvement

机译:TSV铜镀层间隙填充改进的有效方法

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TSV (Through Silicon Via) is a new method for 3D technology (IC integration). Different chips can be connected with the Cu line through silicon substrate. Via area is so deep (usually 100-300um) that we need thicker barrier and seed layer. The Cu plating is the key step in TSV flow. But we suffered TSV void issue in TSV ECD (Electro Chemical Deposition ) process for TSV seed layer poor condition impact .It is important to understand how to improve TSV Cu plating gap fill capability in order to develop TSV technology. In this paper, the barrier and seed layer performance improvement in TSV Cu plating is introduced, and then an effective approach to improve the TSV plating gap fill capability is demonstrated.
机译:TSV(硅通孔)是一种用于3D技术(IC集成)的新方法。不同的芯片可以通过硅基板与铜线连接。通孔区域是如此之深(通常为100-300um),因此我们需要更厚的阻挡层和种子层。镀铜是TSV流程中的关键步骤。但是由于TSV种子层不良条件的影响,我们在TSV ECD(电沉积)工艺中遇到了TSV空洞问题。了解如何提高TSV Cu镀层间隙填充能力对于开发TSV技术至关重要。本文介绍了TSV Cu镀层中阻挡层和籽晶层性能的改进,然后提出了一种提高TSV镀层间隙填充能力的有效方法。

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