A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators

摘要

A dataflow graph is a computation abstraction with explicit dependencies that can be automatically parallelized. This work focuses on mapping dataflow graphs onto reconfigurable architectures and exploring them when fully pipelined. To embed these graphs onto mesh-based architectures, we propose a flexible mapping approach based on simulated annealing. We also implement a GPU parallel mapping to mitigate the mapping time. The trade-offs of target architectures areas are evaluated by exploring different interconnection topologies and local delay FIFOs on FPGAs and ASICs. To quickly evaluate different architectures, we developed a parameterized hardware generator that outputs costs in terms of wire length and buffer costs. We also propose a novel interconnection topology, called Chess. In comparison to other state-of-the-art mapping tools, including CGRA-ME, SAT solvers and VPR, our main contributions are: (a) finding optimal or near-optimal fully pipelined mappings; (b) scaling the dataflow graph size up to 70 operators without FIFOs; (c) proposing a framework to perform a design exploration of mesh architectures and more complex interconnection topologies.