首页>
外国专利>
Pipeline depth exploration in a register transfer level design description of an electronic circuit
Pipeline depth exploration in a register transfer level design description of an electronic circuit
展开▼
机译:电子电路寄存器传输级设计中的管道深度探索
展开▼
页面导航
摘要
著录项
相似文献
摘要
A list of input registers and output registers for a circuit design are provided. The circuit design is modified by traversing output connections paths for each input register and replacing any register in the output connection paths with a wire unless the register is a listed output register. An initial total cycle time value for the modified circuit design is determined. A gate level description for the modified circuit design is obtained by a macro synthesis with the initial total cycle time value. The total cycle time value for the modified circuit design is then varied in order to determine the theoretical limit of the modified circuit design. This theoretical limit is realized when negative slacks are present in a macro synthesis of the modified circuit design for a given total cycle time value. Based on this theoretical limit, the minimum pipeline depth of the circuit design is determined.
展开▼