FDSOI process/design full solutions for ultra low leakage, high speed and low voltage SRAMs

摘要

We propose for the first time a complete SRAM offer in FDSOI technology, covering low leakage, high speed and low voltage customer requirements, through simple and innovative process/design solutions. Starting from a bulk-design direct porting, we evidenced +50% and +200% Iread at Vdd=1V and 0.6V, respectively vs 28LP bulk. Additionally, −100mV Vmin reduction has been demonstrated with 28FDSOI. Alternative flip-well and single well architecture provides further speed and Vmin improvement, down to 0.42V on 1Mb 0.197µm2. Ultimate stand-by leakage below 1pA on 0.120µm2 bitcell at Vdd=0.6V is finally reached by taking the full benefits of the back bias capability of FDSOI.