ABSTRACT An ultra low leakage SRAM Cell is disclosed at the 65nm node. Process and circuit techniques are used together to achieve extremely low leakage in standby mode while still maintaining the high read current in active mode. We demonstrate an ultra low ISB of 0.52pA/cell in the standby retention mode and a simultaneous read current of 17.5uA/cell. The 4-way halo is replaced by a 2-way halo for the Cell FETs to minimize GIDL which is found to be the dominant component of overall leakage. In addition, circ uit techniques such as source biasing are used to achieve ultra low leakage without trading off too much on the access time and Static Noise Margin across all operating temperatures. Due to the above modifications this special cell, which is unique in the indu stry, is able to work as a dual mode cell capable of both fast Async as well as MoBL operation. This enables Cypress to get enhanced yield for its Asynchronous memory products in 65nm. The learning from this will also be extended to the 55nm node (for S55 platform) which will give us an additional 20% saving in SRAM cell area.
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