Optimization of mask manufacturing rule check constraint for model based assist feature generation

摘要

SRAF (sub-resolution assist feature) generation technology has been a popular resolution enhancement technique in photo-lithography past sub-65nm node. It helps to increase the process window, and these are some times called ILT(inverse lithography technology). Also, many studies have been presented on how to determine the best positions of SRAFs, and optimize its size. According to these reports, the generation of SRAF can be formulated as a constrained optimization problem. The constraints are the side lobe suppression and allowable minimum feature size or MRC (mask manufacturing rule check). As we know, bigger SRAF gives better contribution to main feature but susceptible to SRAF side lobe issue. Thus, we finally have no choice but to trade-off the advantages of the ideally optimized mask that contains very complicated SRAF patterns to the layout that has been MRC imposed applied to it. The above dilemma can be resolved by simultaneously using lower dose (high threshold) and cleaning up by smaller MRC. This solution makes the room between threshold (side lobe limitation) and MRC constraint (minimum feature limitation) wider. In order to use smaller MRC restriction without considering the mask writing and inspection issue, it is also appropriate to identify the exact mask writing limitation and find the smart mask constraints that well reflect the mask manufacturability and the e-beam lithography characteristics.In this article, we discuss two main topics on mask optimizations with SRAF. The first topic is on the experimental work to find what behavior of the mask writing ability is in term of several MRC parameters, and we propose more effective MRC constraint for aggressive generation of SRAF. The next topic is on finding the optimum MRC condition in practical case, 3X nm node DRAM contact layer. In fact, it is not easy to encompass the mask writing capability for very complicate real SRAF pattern by using the current MRC constraint based on the only width and space restriction. The test mask for this experimental work includes not only typical split patterns but also real device patterns that are generated by in-house model-based assist feature generation tool. We analyzed the mask writing result for typical patterns and compared the simulation result, and wafer result for real device patterns.