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Cu Pillar Bump FCBGA Package Design and Reliability Assessments

机译:铜支柱凸点FCBGA封装设计和可靠性评估

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With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it's also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as "Cu pillar bump" with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material.This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bumpstructure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.
机译:随着电子消费产品向更多功能,高性能和小型化发展的趋势,要求IC芯片在相同的封装尺寸下提供更多的输入/输出(I / O)和更好的电气特性。倒装芯片BGA(FCBGA)封装是为了满足这些要求而开发的,这些要求具有更好的电气性能,更多的I / O引脚容纳能力和较高的传输速度。但是,倒装芯片技术正遇到其结构限制,因为凸点间距越来越小,因为球形几何形状的凸点形状会限制精细的凸点间距排列,并且也难以通过窄间隙之间的底部填充来填充。根据这种需求,开发了一种新的精细凸点间距技术,即具有铜柱和焊嘴结构的“铜柱凸点”。铜柱凸块是电镀工艺制造的结构,由铜圆柱(铜柱)和蘑菇形焊帽(焊锡尖)组成。铜柱凸块的几何形状不仅提供了更细的凸块间距,而且由于比传统的焊接材料具有更高的导电性,还提高了热性能。 本文主要通过有限元模型来表征FCBGA封装的Cu柱凸点结构应力性能,以防止可靠性失效。首先,研究了铜柱凸点的凸点应力和Cu / low-k应力,以与常规凸点进行比较。 结构体。目的是研究铜柱凸块结构的潜在可靠性风险。其次,评估了不同聚酰亚胺(PI)层,凸块下金属化(UBM)尺寸和阻焊层开口(SMO)尺寸的凸点应力和Cu / low-k应力分布。这项研究可以显示每个设计因素的应力贡献。第三,研究了结合UBM尺寸,Cu柱厚,SMO尺寸,PI开口和PI厚度的基体,观察了应力分布。最后,通过可靠性测试对应力模拟结果进行了实验验证。

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