Thermal Cycling Reliability of Cu/SnAg Double-Bump Flip-chip Assemblies for 100um Pitch Applications

摘要

Thick Cu column based double-bump flip-chip structure is one of the promising alternatives for fine pitch flip-chip applications. In this study, the thermal cycling (T/C) reliability of Cu/SnAg double-bump flip-chip assemblies was mainly investigated and the failure mechanism was analyzed through the correlation of T/C test results and the finite element analysis (FEA). T/C failures occurred from the outmost Cu/SnAg flip-chip joints with largest distance of the neutral point (DNP) of a chip. After 1000 cycles, all of the failures occurred at about 4～7 Cu/SnAg joints located at the edge and corner of a chip. SAM (scanning acoustic microscope) analysis and SEM (scanning electron microscope) observation indicated that the failure site was Cu column/Si chip interface and the displacement of Al and Ti layer of Cu/Si interface due to large compressive stress. From the FEA, the maximum stress was concentrated at Cu column/Si chip interface during thermal cycling. From the low cycle fatigue model, the accumulation of the equivalent plastic strain resulted in the thermal fatigue deformation of Cu column bumps and finally reduced the thermal cycling lifetime. As the number of thermal cycles increased, the maximum equivalent plastic strains of each joint increased at from the outmost joints to the 4th ～ 7th joints which showed T/C failures after 1000 cycles. However, equivalent plastic strains did not increase regardless of thermal cycles. In addition, a normal stress of y-direction, S_(22) was a dominant component determining overall stress of Cu/SnAg flip-chip joints and it was compressive. During thermal cycling, the compressive normal stress in low temperature region was mainly inflicted on Cu column bumps in perpendicular direction (y-direction in 2-D FEA) to a chip and Cu column bumps. As a result, the displacement failure of Al and Ti layer, the main T/C failure mode of Cu/SnAg flip-chip assembly, occurred between Si chip and Cu column interface by the compressive normal stress.