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Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation

机译:利用约束组合固定测试生成加速非循环时序电路的过渡测试生成

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This paper presents a transition test generation method for acyclic sequential circuits. In this method, to generate test sequences for transition faults in a given acyclic sequential circuit, constrained combinational stuck-at test generation is performed on its double time-expansion model that is composed of two copies of a time-expansion model of the given circuit. This method is complete, i.e., this method can generate test sequences for all the testable transition faults and can identify all the untestable transition faults in a given acyclic sequential circuit. Experimental results show that our method can achieve higher fault efficiency with drastically shorter test generation time than that achieved by a conventional method.
机译:本文介绍了用于无循环顺序电路的过渡试验方法。在该方法中,为了在给定的无环顺序电路中生成用于转换故障的测试序列,对其双时扩展模型进行约束组合卡在测试生成,其由给定电路的时间扩展模型的两份副本组成。该方法是完整的,即,该方法可以为所有可测试的过渡故障生成测试序列,并且可以识别给定的无环顺序电路中的所有不可发出的过渡故障。实验结果表明,我们的方法可以通过传统方法实现的较短的测试生成时间来实现更高的故障效率。

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