Combinational test generation for sequential circuits.

摘要

Electronic revolution by way of increasing density and features of VLSI circuits is enabling more complex design on circuits. This coupled with high reliability requirement at low cost is forcing the VLSI design and test engineers to consider more efficient methods of testing digital circuits.; In this dissertation, first, a method of generating tests for sequential circuits using a more efficient combinational Automatic Test Pattern Generation programs is proposed. Second, a comprehensive study of available methods to aid and to generate combinational test generation models are studied and investigated. Third, a generalized single stuck-at fault model for multiple faults and its applications, including fault diagnosis, circuit optimization, bridging fault modeling and testing of multiply-testable faults are addressed.