New constraint for Vth optimization for sub 32nm node CMOS gates scaling

摘要

We show new constraint of V_th scaling for logic blocks from inverter operation viewpoint. In lower V_th region, delay time in inverter chain saturates because of the loss in overdrive for the input of MOSFETs. This loss dominates the inverter speed in scaled V _dd region and we propose a new relaxed scaling scenario. This accounts for the speed loss using a simplified model which adequately manifests the new phenomenon