New Constraint for Vth Optimization for Sub 32nm Node CMOS Gates Scaling

摘要

We show new constraint of V{sub}(th) scaling for logic blocks from inverter operation viewpoint. In lower V{sub}(th) region, delay time in inverter chain saturates because of the loss in overdrive for the input of MOSFETs. This loss will dominate the inverter speed in scaled V{sub}(dd) region and we propose a new relaxed scaling scenario. This accounts for the speed loss using a simplified model which adequately manifests the new phenomenon.