Charge trapping in MOCVD hafnium-based gate field dielectric stack structures and its impact on device performance

摘要

Threshold voltage instability and mobility degradation are significant issues for high-k dielectrics. The impact of interfacial and bulk high-k properties on these issues was investigated using Hf-based gate dielectric stacks of varying physical thickness with polysilicon electrodes. The impact of charge trapping on device performance was characterized by electrical and physical analysis. Results suggest that the bulk trapping in the high-k film contributes to the degradation of device performance.