A Novel NMOS transistor for High Performance ESD Protection Devices in 0.18 mum CMOS Technology Utilizing Salicide Process

摘要

The electrostatic discharge (ESD) threshold of fully salicided grounded-gate NMOS transistors (ggNMOSTs) and partially salicided ggNMOSTS consisting dummy-gate and N-well resistor was studied by transmission line pulse (TLP) I-V curves, HBM and MM robustness. The state-of-the-art 0.18-mum-cobalt-salicide CMOS process is used, and the thickness of gate-dielectric material is 35A. Fully salicided ggNMOSTs have much lower values of second breakdown current (It2) than partially salicided ggNMOSTs, and with multi-finger structures only partially salicided ggNMOSTs turn on uniformly. Using these partially salicided NMOSTs as protection devices we acquired ESD immunity of >2kV (HBM) and >200V (MM).