【24h】

Area array packages - materials requirements for diminishing devices

机译:区域阵列封装-缩小设备的材料要求

获取原文

摘要

Continuously increasing proprtion of both consumer and professional electronic devices is portable enabling users to take advantage, for example, of e-mail or browse internet independently of their location. This requires high performance from the equipment that inevitably implies very high packaging efficiency; more functions and higher performance must be incorporated into an ever-smaller housing. Consequently, new packaging, substrate and interconnection technologies must be developed continuously.Area array packages, especially Chip Scale Package and Flip Chip, can provide close to ideal package size in relation to the integrated circuit size. It follows that also the dimensions of solder joints will be very small as compared to conventional surface mount technology, and thus much research and development work is ennded to overcome the challenges. In addition, printed wirin board design rules are shrinking to be able to perform effective routing for the new components. New manufacturing technologies and materials have to be developed parallel to the component and substrate technologies in order to ensure smooth and reliable assembly operations. This paper reviews challenges that the new technologies set on materials and presents some viable new solutions.
机译:消费电子产品和专业电子设备的不断增长的便携性使用户能够利用电子邮件或独立于其位置浏览互联网等优势。这需要设备的高性能,这不可避免地意味着很高的包装效率。越来越小的功能必须结合更多的功能和更高的性能。因此,必须不断开发新的封装,基板和互连技术。面积阵列封装,尤其是芯片级封装和倒装芯片,相对于集成电路尺寸而言,可以提供接近理想的封装尺寸。因此,与传统的表面安装技术相比,焊点的尺寸也将非常小,因此需要进行大量的研究和开发工作来克服这些挑战。此外,印刷的wirin板设计规则正在缩小,以便能够为新组件执行有效的布线。必须与组件和基板技术并行开发新的制造技术和材料,以确保平稳可靠的组装操作。本文回顾了新技术对材料提出的挑战,并提出了一些可行的新解决方案。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号