首页> 外国专利> Optimization of routing layers and board space requirements for ball grid array package implementations including array corner considerations

Optimization of routing layers and board space requirements for ball grid array package implementations including array corner considerations

机译:球栅阵列封装实现的布线层和电路板空间要求的优化,包括阵列角点的考虑

摘要

A method and apparatus for improved contact pad arrays and land patterns for integrated circuit packages are presented. A plurality of conductive pads are arranged in an array of rows and columns. At least one edge of a perimeter of the array is not fully populated with conductive pads. Spaces created in the edge by missing conductive pads create additional routing channels for signals from conductive pads within the array to be routed external to the array through the edge. A land pattern may have routing channels on one or more layers of a printed circuit board. In such a multi-layer land pattern, spaces can be created in edges on any number of the layers. Furthermore, corner pad arrangements having known routing channel characteristics can be used in any number of corners of a land pattern that incorporates spaces in an edge.
机译:提出了一种用于集成电路封装的改进的接触垫阵列和焊盘图案的方法和装置。多个导电焊盘以行和列的阵列布置。阵列周边的至少一个边缘没有完全填充导电垫。由于缺少导电焊盘而在边缘中产生的空间为来自阵列内导电焊盘的信号提供了额外的路由通道,这些信号将通过边缘路由到阵列外部。焊盘图案可在印刷电路板的一层或多层上具有布线通道。在这种多层焊盘图案中,可以在任意数量的层的边缘中创建空间。此外,具有已知的布线通道特性的角垫装置可以用在结合在边缘中的空间的焊盘图案的任何数量的角中。

著录项

  • 公开/公告号US2005044517A1

    专利类型

  • 公开/公告日2005-02-24

    原文格式PDF

  • 申请/专利权人 KEVIN L. SEAMAN;VERNON M. WNEK;

    申请/专利号US20040951914

  • 发明设计人 VERNON M. WNEK;KEVIN L. SEAMAN;

    申请日2004-09-29

  • 分类号G06F9/45;

  • 国家 US

  • 入库时间 2022-08-21 22:22:12

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号