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New data processing of dummy pattern generation adaptive for CMP process

机译:适用于CMP工艺的虚拟图案生成的新数据处理

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Abstract: For planarization of interlevel dielectric between two wiring layers, chemical mechanical polishing (CMP) is used from 0.25 micrometer devices. Here, in order to improve global planarity, dummy patterns area added to the original wiring patterns. In the conventional dummy generation system, because the all wiring patterns are oversized geometrically to obtain CMP area, the geometrical oversizing consumes a long time. In order to reduce the time of geometrical oversizing, minimum CMP area and maximum CMP area, which is calculated faster than geometrical oversizing, are introduced in the new data processing. At first, instead of the geometrical oversizing, the total area of patterns (minimum CMP area) and the total area of individually oversized patterns (maximum CMP area) are calculated at each small region in wiring layer. Then dummy generation regions are selected by using these two total area. When all of surroundings of a small region are decided to be dummy generation region or not, the geometrical oversizing can be omitted at the small region. As the number of regions at which the geometrical oversizing is omitted increases, the data processing time of dummy pattern generation improves significantly. As the result, using a sample data: 0.25 micrometer ASIC device wiring data with about 50 million figures, the processing time of as fast as about 1 hour 30 minutes has been achieved by the new system compared to about 2 hours and 10 minutes with the conventional system. This improvement of the processing time contributes to shorten TAT of mask data processing for ULSI. !0
机译:摘要:为了平坦化两个布线层之间的层间电介质,使用了0.25微米器件的化学机械抛光(CMP)。在此,为了改善整体平面性,在原始配线图案上增加了虚设图案区域。在常规的虚拟生成系统中,由于所有布线图案在几何上都尺寸过大以获得CMP区域,因此几何尺寸过大会花费很长时间。为了减少几何尺寸过大的时间,在新数据处理中引入了比几何尺寸过大的计算速度更快的最小CMP区域和最大CMP区域。首先,代替几何尺寸过大,在布线层中的每个小区域计算图案的总面积(最小CMP面积)和各个尺寸过大的图案的总面积(最大CMP面积)。然后,通过使用这两个总面积来选择虚拟生成区域。当将小区域的所有周围环境都确定为不是虚拟产生区域时,可以在小区域处省略几何尺寸过大。随着省略几何尺寸过大的区域的数量增加,虚拟图案生成的数据处理时间显着提高。结果,使用示例数据:0.25微米的ASIC器件布线数据(约有5000万个数字),新系统已实现了大约1小时30分钟的处理时间,而使用新系统的时间约为2小时10分钟。常规系统。处理时间的这种改善有助于缩短用于ULSI的掩码数据处理的TAT。 !0

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