The continued scaling of Si MOSFET faces many critical issues. In this paper, the authors discuss drain architecture in relation to performance and the possibility of sub-0.1 /spl mu/m CMOS devices. It is found that an abrupt junction is indispensable for source/drain (S/D) extension to obtain higher drain current capability. On the other hand, a graded junction is desirable for deep S/D to decrease the junction capacitance. The drain architecture combined with doping technology such as plasma doping and spike anneal is one of the most important solutions for sub-0.1 /spl mu/m MOSFETs.
展开▼
机译：Si MOSFET的持续缩放面临许多关键问题。在本文中，作者讨论了与性能有关的漏极架构以及sub-0.1 / spl mu / m CMOS器件的可能性。发现突然的结对于源/漏（S / D）扩展以获得更高的漏电流能力是必不可少的。另一方面，对于深S / D而言，渐变结是理想的，以减小结电容。漏极架构与等离子掺杂和尖峰退火等掺杂技术相结合，是低于0.1 / spl mu / m MOSFET的最重要解决方案之一。
展开▼
