Validation of yield models with CMOS/SOS test structures

摘要

A methodology assessed to implement wafer level reliability relies on the design of specific test structures which must be as similar as possible to functional circuits geometries and lay-outs. In a second step, electrical tests provide wafer level data to validate the use of the Poisson yield model which gives defect densities. It is found that chips from the central area of the wafer present randomly distributed defects whereas those from the periphery are governed by a more systematic distribution.