A multichip module process using flipped-chip interconnections is discussed. The process uses plated copper bumps for superior thermal transport characteristics, active silicon as a substrate material for matched expansion properties, and on-chip interconnection metallization that allows bumps to be placed over the active circuitry. It also makes use of conventional wafer fabrication facilities, allowing low-cost production. Details of the fabrication process are described, modeling and design verification are discussed, and a demonstration example is given.
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