A Design Flow for Micro Bump and Stripe Planning on Modern Chip-Package Co-Design

摘要

Micro bumps and stripes play essential roles for the transmission of signals and the preservation of power integrity in the modern flip-chip packaging process. For different placement block designs on a chip, the best micro bump arrangement and stripe generation method is usually varied accordingly. It often takes a lot of manpower and time cost in generating the delivery path of signal and power transmission in a package. As a result, we propose a way that can automatically generate a power delivery network (PDN) on the top metal layers in a chip and set the coordinate of micro bumps. It can solve the IR drop problem in the early stage, and decrease the integrated circuit (IC) and packaging layout design iteration, thus shorten time-to-market (TTM). Experimental results show that our flows can reduce IR drop to 5% of supply voltage in block.