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Characterisation, Modelling and Design of Bond-Wire Interconnects for Chip-Package Co-Design Insertion Loss (dB)

机译:用于芯片封装共同设计插入损耗(dB)的键合线互连的特性,建模和设计

摘要

This work is a comprehensive experimental investigation of chip to package wirebond interconnects for chip-package co-design. Wirebonds are interconnect bottlenecks in RF design, but are difficult to avoid due to their low cost and manufacturing ease. We have shown measurements on wirebonds in coplanar configuration with different return paths and also the cross coupling. We have also extracted lumped and distributed models and demonstrate the excellent agreement with measurements atleast upto 15GHz. We have proposed multi-wirebonds as a potential solution for better impedance matching. Different types of inductors with Q-factors of upto 100 have also been illustrated. We show influence of encapsulant on wirebonds and finally we also demonstrate a methodology to extract the time-domain response from S-parameters.
机译:这项工作是对芯片到封装引线键合互连进行芯片-封装协同设计的全面实验研究。引线键合是射频设计中的互连瓶颈,但由于其成本低和易于制造而难以避免。我们已经显示了共面配置中具有不同返回路径以及交叉耦合的引线键合的测量结果。我们还提取了集总模型和分布式模型,并证明了其在至少15GHz的测量条件下的出色一致性。我们提出了多线键合作为更好阻抗匹配的潜在解决方案。还已经说明了Q因子高达100的不同类型的电感器。我们展示了密封剂对引线键合的影响,最后我们还展示了一种从S参数中提取时域响应的方法。

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